JPH0461387B2 - - Google Patents
Info
- Publication number
- JPH0461387B2 JPH0461387B2 JP62121507A JP12150787A JPH0461387B2 JP H0461387 B2 JPH0461387 B2 JP H0461387B2 JP 62121507 A JP62121507 A JP 62121507A JP 12150787 A JP12150787 A JP 12150787A JP H0461387 B2 JPH0461387 B2 JP H0461387B2
- Authority
- JP
- Japan
- Prior art keywords
- bus
- data
- clock
- permission signal
- timing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
- G06F13/376—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a contention resolving method, e.g. collision detection, collision avoidance
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62121507A JPS63285658A (ja) | 1987-05-19 | 1987-05-19 | バス上のデ−タ衝突防止回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62121507A JPS63285658A (ja) | 1987-05-19 | 1987-05-19 | バス上のデ−タ衝突防止回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63285658A JPS63285658A (ja) | 1988-11-22 |
JPH0461387B2 true JPH0461387B2 (en]) | 1992-09-30 |
Family
ID=14812907
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62121507A Granted JPS63285658A (ja) | 1987-05-19 | 1987-05-19 | バス上のデ−タ衝突防止回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63285658A (en]) |
-
1987
- 1987-05-19 JP JP62121507A patent/JPS63285658A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS63285658A (ja) | 1988-11-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
RU2140667C1 (ru) | Компьютерная система, имеющая шинный интерфейс | |
EP0476990B1 (en) | Dynamic bus arbitration | |
US5119480A (en) | Bus master interface circuit with transparent preemption of a data transfer operation | |
US6151651A (en) | Communication link with isochronous and asynchronous priority modes coupling bridge circuits in a computer system | |
JP3860209B2 (ja) | 直列割込みバス・プロトコル | |
US6282598B1 (en) | PCI bus system wherein target latency information are transmitted along with a retry request | |
JPS6015765A (ja) | 共通バスのアクセス制御システム | |
JPH09212447A (ja) | Pcmciaカード上の割り込み共有技術 | |
US5287486A (en) | DMA controller using a programmable timer, a transfer counter and an or logic gate to control data transfer interrupts | |
US6032204A (en) | Microcontroller with a synchronous serial interface and a two-channel DMA unit configured together for providing DMA requests to the first and second DMA channel | |
US5539916A (en) | DMA control for continuing transfer to input/output device in a cycle steal mode | |
EP0473453B1 (en) | Work station having a selectable CPU | |
US4180855A (en) | Direct memory access expander unit for use with a microprocessor | |
US5446847A (en) | Programmable system bus priority network | |
JPH0461387B2 (en]) | ||
KR101276837B1 (ko) | 서로 다른 동작 주파수로 동작하는 프로세서 시스템 간의 통신을 지원하기 위한 장치 | |
KR950008393B1 (ko) | 멀티프로세스 시스템 아비터지연회로 | |
JP2565916B2 (ja) | メモリアクセス制御装置 | |
KR100243868B1 (ko) | 주 전산기에서의 중재로직 방법 | |
JPS6269348A (ja) | デ−タ転送装置 | |
JP2632049B2 (ja) | マルチプロセッサシステム | |
JP2667285B2 (ja) | 割込制御装置 | |
JP2882341B2 (ja) | 共有資源アクセス調停方式 | |
JPH0142010B2 (en]) | ||
JPH0434187B2 (en]) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |